An embodiment of the present invention relates to the field of integrated circuits, and, more particularly, to an approach for reducing power consumption of integrated circuits.
Power consumption of integrated circuits and, in particular, complex integrated circuits, such as microprocessors, is becoming a significant concern. This is especially true for current and future technology generations for which leakage power consumption is a significant percentage of total power consumption.
For some prior approaches, to address this issue, the frequency and supply voltage of a processor are both varied according to an activity level of the processor in order to reduce power while maintaining a relatively constant perceived throughput. This approach, however, typically requires changes to the operating system to predict when high-frequency operation will be necessary. At the same time, continually changing the clock frequency adds complexity to the design.